It is well known to temporarily store data, arriving from one portion of a data processing machine, until that data is needed by a subsequent machine portion; generally, the first item of data received at the temporary memory input is the first item made available at the output. This First-In/First-Out, or FIFO, form of temporary storage is particularly attractive in situations where data at differing clock speeds must be interfaced, or where processing times for each data item may be different, so that the subsequent processor is configured to call for the next data item only when ready, rather than on a clock-only basis. Thus, when the receiving process is not ready for data, the sending process must wait and store data that is ready to be sent. Data transmission between the two processes will resume when the receiving process is ready. If the sending process does not have data to send, the receiving process must wait until data is available.
Referring to FIG. 1, perhaps the first form of temporary storage of this type may have been a shift register 10, having N plural stages 10a-10n, interconnected so as to facilitate data items, entering an input 10I, shifting though the sequential stages responsive to at least one shift clock signal, until the items appear in the same order at the register output 10o. Of course, those skilled in the art will immediately recognize that many problems will occur with such a simple FIFO, not the least of which is the need for at least two separate clock signals, i.e. an input clock CLK0 at input 10x-1 to shift into storage the new data bit then present at the stage input, after the stored previous data was cleared from that stage by operation of an output clock CLK1 at input 10x-2 to first shift the stored data bit to the output of that stage. This form of FIFO is said to be synchronous, in that all data will be shifted simultaneously; such operation is often not desired.
The prior-art FIFO 12 of FIG. 1a solved many of the shift-register-FIFO 10 problems: a stack of N data word registers 14a-14n all receive the incoming data word at common FIFO input port 14I, but only that resistor 14 then enabled by a write signal at its input 14Sw (where S is the stage number A to N) will accept the data word for storage. The write signal is provided at a mutually-exclusive one of the N outputs 15-10 of a write counter means 15-1, which cyclically counts through all N counts, responsive to a write-enable WR.sub.-- EN signal at input 15-1a. Thus, the rate at which new data words are stored in the unit is governed by the rate of pulsatile signals at input 15-1a; the count can be reset to a preselected state (say, zero) by operation of a reset input 15-1b. All of the N registers 14a-14n have an output connected to a common FIFO output port 14o, but only that stage 14 then enabled by a read signal at its input 14Sr will output its stored data word for subsequent use. The read signal is provided at a mutually-exclusive one of the N outputs 15-20 of a read counter means 15-2, which cyclically counts though all N counts, responsive to a separate read-enable RD.sub.-- EN signal at input 15-2a. Thus, the rate at which stored data words are output from unit 12 is governed by the rate of pulsatile signals at input 15-2a; this count can also be reset to a preselected state (say, zero) by operation of its independent reset input 15-2b. If the WR.sub.-- EN signal at input 15-1a is different from the RD.sub.-- EN signal at input 15-2a, the FIFO can input and output data words upon occurrence of different events and at different frequencies. Those skilled in the art will recognize that while FIFO 12 solves some of the register 10 problems, there are still problems, such as overflow, underflow, and the like, with FIFO 12.
Another prior-art FIFO 20 (FIG. 1b) solves most of these problems. In FIFO 20, a multi-dataword storage memory means 22 will store a new data word, input at FIFO input port 20a, responsive to the presence of both a write clock wr-clk signal at input 20c and a write-enable wr-en signal at input 20d; the pair of signals advances the count in a first counter means 24-1, which count is coupled (via a first exclusive-OR gate 26-1 acting on the two most significant address bits (MSBs 1&2)) via bus A, to the wr-addr input of the memory means 22. A first synchronizer means 28-1, comprised of a pair of type-D flip-flops, also receives the first counter means 24-1 output data. The data words stored in memory 22 are individually read to means output 20b responsive to the presence of a cyclic read address rd-addr signal, from the output bus of another counter means 24-2, which is cyclically provided responsive to a read clock rd-clk signal at an input 20e and a read enable rd-en signal at an input 20f. The second counter output bus is also connected to another synchronizer means 28-2. A first comparator means 30-1 receives the first synchronizer output and the second counter means output to determine if the memory is empty, and responsively provides a suitable signal at output 20g. A second comparator means 30-2 as well as gating logic means 32 acts upon the second synchronizer output and the first counter means output to determine if the FIFO memory means 22 is full; output 20h is enabled when the FIFO is full, so that further data input can be temporarily suspended.
The memories described hereinabove are useful, but all have some form of shortcoming. Even the synchronized FIFO of FIG. 1b, while solving many of the prior problems, still does not allow the content of any temporarily-stored dataword to be accessed and/or be altered while the queue of words is in storage; these features are often desirable. Accordingly, we desire to provide a FIFO in which the contents of any stored dataword can be addressed, accessed and changed or removed, if desired, without changing the first-in, first-out basic operation of the memory.